Keynote speakers

 

Andreas Peter Burg (EPFL, Lausanne)

Approximate Computing for Unreliable Silicon

Approximate Computing is frequently mentioned as a new computing paradigm that enables improving energy efficiency at the expense of quality. But what is Approximate Computing? How can it be used in a truly innovative way that goes beyond reducing precision or approximating complex operations or algorithms at the expense of accuracy as it is already done regularly in the VLSI signal processing community for implementing complex video, audio, or communication systems?

In this talk, we focus on Approximate Computing as a new paradigm to deal specifically with one of the most important problems of the semiconductor industry today: the reliability issues and uncertainties in modern process technologies that appear especially at low voltages. We show how Approximate Computing can and should be interpreted as a systematic  idea of dealing with these reliability issues that are statistical in nature and appear only at run-time. In this sense, the interpretation of the term is significantly different from the static design-time interpretation of the term used in the VLSI signal processing community. Approximations and corresponding circuits serve as a means to ensure graceful performance degradation at run-time in the presence of uncertainties or errors, rather than simply reducing complexity once at design time. This ability then allows not only for circuits with reduced area and  better energy efficiency. It also enables better overall performance metrics since each chip delivers at every moment of its life the best possible (adjustable) energy and quality trade off with an energy-proportional behavior adjusted to its operating conditions and user demands.

 

BIOGRAPHY: Andreas Burg (S'97-M'05) was born in Munich, Germany, in 1975. He received his Dipl.-Ing. degree from the Swiss Federal Institute of Technology (ETH) Zurich, Zurich, Switzerland, in 2000, and the Dr. sc. techn. Degree from the Integrated Systems Laboratory of ETH Zurich, in 2006.

In 1998, he worked at Siemens Semiconductors, San Jose, CA. During his  doctoral studies, he worked at Bell Labs Wireless Research for a total of one year. From 2006 to 2007, he held positions as postdoctoral researcher at the Integrated Systems Laboratory and at the Communication Theory Group of the ETH Zurich. In 2007 he co-founded Celestrius, an ETH-spinoff in the field of MIMO wireless communication, where he was responsible for the ASIC development as Director for VLSI. In January 2009, he joined ETH Zurich as SNF Assistant Professor and as head of the Signal Processing Circuits and Systems group at the Integrated Systems Laboratory. Since January 2011, he has been a Tenure Track Assistant Professor at the Ecole Polytechnique Federale de Lausanne (EPFL) where he is leading the Telecommunications Circuits Laboratory.

In 2000, Mr. Burg received the Willi Studer Award and the ETH Medal for his diploma and his diploma thesis, respectively. Mr. Burg was also awarded an ETH Medal for his Ph.D. dissertation in 2006. In 2008, he received a 4-years grant from the Swiss National Science Foundation (SNF) for an SNF Assistant Professorship.

He has served on the TPC of various conferences on VLSI, signal processing, and communications. He was a TPC co-chair for VLSI-SoC 2012 and is a TCP co-chair ESSCIRC 2016 and for SiPS 2017. He served as an Editor for the IEEE Transaction of Circuits and Systems in 2013 and is on the Editorial board of the Springer Microelectronics Journal and the MDPI Journal on Low Power Electronics and its Applications.

 

Ozgur Sinanoglu (NYU Abu Dhabi)

Do You Trust Your Chip?

Globalization of Integrated Circuit (IC) design and manufacturing is making designers and users of ICs re-assess their trust in hardware. As the IC design flow spans the globe - driven by cost-conscious consumer electronics - hardware is increasingly prone to reverse engineering, Intellectual Property (IP) piracy and malicious modifications (i.e., hardware trojans). An attacker, anywhere within the global design flow, can reverse engineer the functionality of an IC/IP, steal and claim ownership of the IP or introduce counterfeits into the supply chain. Moreover, an untrusted IC fab may overbuild ICs and sell them illegally. Finally, rogue elements in the fabs may insert hardware trojans into the design without the knowledge of the designer or the end-user of the IC; this additional functionality may subsequently be exploited to introduce errors in the results, steal sensitive information or incapacitate a fielded system. The semiconductor industry routinely loses $billions annually due to these attacks. This talk will cover various forms of threats that the electronic chip supply chain is up against, as well as defenses against these threats. The talk will elucidate the development of CAD algorithms/tools for this newly emerging field by mostly leveraging principles from other more mature research domains.

BIOGRAPHY: Ozgur Sinanoglu is an associate professor of electrical and computer engineering at New York University Abu Dhabi. He earned his B.S. degrees, one in Electrical and Electronics Engineering and one in Computer Engineering, both from Bogazici University, Turkey in 1999. He obtained his MS and PhD in Computer Science and Engineering from University of California San Diego in 2001 and 2004, respectively. He has industry experience at TI, IBM and Qualcomm, and has been with NYU Abu Dhabi since 2010. During his PhD, he won the IBM PhD fellowship award twice. He is also the recipient of the best paper awards at IEEE VLSI Test Symposium 2011 and ACM Conference on Computer and Communication Security 2013. 

Prof. Sinanoglu's research interests include design-for-test, design-for-security and design-for-trust for VLSI circuits, where he has more than 140 conference and journal papers, and 15 issued/pending US Patents. Sinanoglu has given more than a dozen tutorials on hardware security and trust in leading CAD and test conferences, such as DAC, DATE, ITC, VTS, ETS, ICCD, ISQED, etc. He is serving or has served as track/topic chair or technical program committee member in about 15 conferences, and as (guest) associate editor for IEEE TCAD, ACM JETC, IEEE TETC, Elsevier MEJ, JETTA, and IET CDT journals. 

Prof. Sinanoglu is the director of the Design-for-Excellence Lab at NYU Abu Dhabi. His recent research in hardware security and trust is being funded by US National Science Foundation, US Department of Defense, Semiconductor Research Corporation, GlobalFoundries and Mubadala Technology.

 

Ilker Hamzaoglu (Sabanci University, Istanbul)

  

 Low Power Digital Video Compression Hardware Design

There is tremendous growth in the amount of digital video creation and communication with the proliferation of mobile consumer electronic devices such as cellular phones with video capture and display capabilities. This trend will continue with the demand for higher spatial and temporal video resolutions accompanied by 3D and multiview video. Since it is not practical to store or transmit the raw digital video data, it is essential to reduce it with digital video compression. To cope with the vast amount of raw digital video data, digital video compression standards use increasingly more complex algorithms. These algorithms achieve higher compression at the same quality at the expense of significant computational complexity. Therefore, it is essential to design low power digital video compression hardware especially for mobile devices.


In this talk, I will present two sets of power reduction techniques for digital video compression hardware. The
ones in the first set reduce the power consumption with no impact on the video quality. The ones in the second set trade off video quality for power consumption which also enables adjusting video quality based on available energy in the battery of a mobile device for graceful degradation. I will show the impact of these techniques
on the power consumption of digital video compression hardware implementing H.264/AVC and H.265/HEVC standards.


BIOGRAPHY:  Ilker Hamzaoglu received B.S. and M.S. degrees in Computer Engineering from Bogazici University, Istanbul, Turkey in 1991 and 1993, respectively. He received Ph.D. degree in Computer Science from University of Illinois at Urbana-Champaign, IL, USA in 1999. He was awarded W. J. Poppelbaum Memorial Award
for Excellent Research in Computer Hardware by University of Illinois at Urbana-Champaign in 1999 for his PhD thesis.

He worked as a Senior and Principle Staff Engineer at Multimedia Architecture Lab, Motorola Inc. in Schaumburg, IL, USA between August 1999 and August 2003. He is currently an Associate Professor at Sabanci University, Istanbul, Turkey where he is working as a Faculty Member since September 2003.  

His research interests include low power digital hardware design for video processing and compression, System-on-Chip (SoC) ASIC and FPGA design, embedded system design, computer-aided design and test for digital VLSI circuits. He has published more than 75 international conference and journal papers in these areas.

He directed several research projects supported by TUBITAK (The Scientific and Technological Research Council of Turkey). He served as a reviewer for research projects supported by TUBITAK.


He served as a TPC member for several IEEE conferences such as DATE, FPL, ASAP, VLSI-SoC, DASIP, DSD. He is an Editorial
Board Member of IEEE Transactions on Consumer Electronics since July 2011. He is an IEEE Senior Member since July 2012.